数据库 ch4_5m.pptVIP

?未经作者允许，请勿发布该文档！yingqichen@sjtu.edu.cn VHDL Simulation Synthesis Data object Agenda Data Type Data Properties Data Object Operation Agenda Data Type Integer Type Physical Type Floating Point Type Enumeration Type Arrays Recorders Subtypes Data Properties Data Object Operation Integer Type Definition Type IntTypeName is range Int1 to Int2 (Int1 and Int2 are integers and Int1 Int2) Type IntTypeName is range Int1 downto Int2 (Int1 and Int2 are integers and Int1 Int2) Integer Type Example Example Type byte_int is range 0 to 255 Type signed_byte is range -128 to 127; Type Bit_idx is range 7 downto 0; Pre-defined type (standard.vhd) TYPE INTEGER IS RANGE -2147483648 TO 2147483647; Integer Signal Example signal a: integer; … a = 1; -- ? a = -1; -- ? a = 1.0; -- ? a = 1 ns; -- ? Agenda Data Type Integer Type Physical Type Floating Point Type Enumeration Type Arrays Recorders Subtypes Data Properties Data Object Operation Physical Type Definition type NewName is range Int1 to Int2 units UnitName1; UnitName2 = ??? UnitName1; UnitName3 = ??? UnitName2; UnitName4 = ??? UnitName3; ... ; end units [NewName]; Physical Type Example (Time) TYPE TIME IS RANGE -9223372036854775808 TO 9223372036854775807 UNITS fs; ps = 1000 fs; ns = 1000 ps; us = 1000 ns; ms = 1000 us; sec = 1000 ms; min = 60 sec; hr = 60 min; END UNITS; Physical Type Example (Resistance) type resistance is range 0 to 1E8 units ohms; kohms = 1000 ohms; Mohms = 1E6 ohms; end units; Physical Type (Package) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; package my_package is constant const_K : integer := 100; type state_type is (idle, s0, s1, s2, s3); subtype Byte is Std_logic_vector(7 downto 0); type Current is range 0 to 1000000000 units nA; uA = 1000 nA; mA = 1000 uA; A = 1000 mA; end units; end my_package;