[英语学习]Converting thread-level parallelism to instruction-level parallelism via simultaneous multi.pdfVIP

Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading JACK L. LO and SUSAN J. EGGERS University of Washington JOEL S. EMER Digital Equipment Corporation HENRY M. LEVY University of Washington REBECCA L. STAMM Digital Equipment Corporation and DEAN M. TULLSEN University of California, San Diego To achieve high performance, contemporary computer systems rely on two forms of parallel- ism: instruction-level parallelism (ILP) and thread-level parallelism (TLP). Wide-issue super- scalar processors exploit ILP by executing multiple instructions from a single program in a single cycle. Multiprocessors (MP) exploit TLP by executing different threads in parallel on different processors. Unfortunately, both parallel processing styles statically partition proces- sor resources, thus preventing them from adapting to dynamically changing levels of ILP and TLP in a program. With insufficient TLP, processors in an MP will be idle; with insufficient ILP, multiple-issue hardware on a superscalar is wasted. This article explores parallel processing on an alternative architecture, simultaneous multithreading (SMT), which allows multiple threads to compete for and share all of the processor’s resources every cycle. The most compelling reason for running parallel applications on an SMT processor is its ability to use thread-level parallelism and instruction-level parallelism interchangeably. By permitting This research was supported by Digital Equipment Corporation, the Washington Technology Center, NSF PYI Award MIP-9058439, NSF grants MIP-9632977, CCR-9200832, and CCR- 9632769, DARPA grant F30602-97-2-0226, ONR grants N00014-92-J-1395 and N00014-94-1- 1136, and fellowships from Intel and the Computer Measurement Group. Authors’ addresses: J. L. Lo, S. J. Eggers, and H. M. Levy, Department of Computer Science and Engineering, Unive