VHDL四位全加器三种语言编程.docVIP

四位全加器的三种VHDL语言描述方式： 一：数据流描述方式 library ieee; use ieee.std_logic_1164.all; entity add1 is port(a,b,cin:in std_logic; s,cout:out std_logic); end add1; architecture dataflow of add1 is begin s=(a xor b) xor cin; cout=((a xor b)and cin)or(a and b); end dataflow; 二：行为描述方式 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity add22 is port(a,b,cin:in std_logic; s,co:out std_logic); end add22; architecture dataflow of add22 is signal tmp:std_logic; begin process(a,b,cin) variable n:integer range 0 to 3; constant s_vector: std_logic