A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications推荐.pdfVIP

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 6, JUNE 2011 1225 A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications Didem Z. Turker, Student Member, IEEE, Sunil P. Khatri, Member, IEEE, and Edgar Sánchez-Sinencio, Life Fellow, IEEE Abstract—In this paper, a low-cost, power efficient and fast The key power-hungry circuits in a frequency synthesizer are Differential Cascode Voltage-Switch-Logic (DCVSL) based delay the voltage-controlled oscillator (VCO) and the frequency di- cell (named DCVSL-R) is proposed. We use the DCVSL-R cell viders [1], especially the programmable dividers that operate at to implement high frequency and power-critical delay cells and flip-flops of ring oscillators and frequency dividers. When com- the RF frequency. Another power hungry block is the RF buffers pared to TSPC, DCVSL circuits offer small input and clock between the VCO and the frequency dividers. Along with fre- capacitance and a symmetric differential loading for previous quency of operation and technology speed, the circuit design RF stages. When compared to CML, they offer low transistor technique of the frequency dividers is key in determining their count, no headroom limitation, rail-to-rail swing and no static current consumption. However, DCVSL circuits suffer from a and their driving buffer’s power consumption. Until recently, large low-to-high propagation delay, which limits their speed Current Mode Logic (CML) circuits [2], [3] were widely em- and results in asymmetrical output waveforms. The proposed ployed in the freq