verilog的文件转换.docVIP

`timescale 1 ns/1 ns `define DEL 2 module tb; //parameter BINFILE = D:/keil/Hello/Obj/hello.bin; parameter BINFILE = E:/Hello/Obj/hello.bin; reg clk = 1b0; always clk = #5 ~clk; reg rst = 1b1; initial #10 rst = 1b0; reg [7:0] rom [8191:0]; integer fd,fx,i,j; initial begin for(j=0;j8192;j=j+1) rom[j]=0; fd = $fopen(BINFILE,rb); fx = $fread(rom,fd); $fclose(fd); fd=$fopen(hello.mem,w); $fdisplay(fd,#Format=Hex); $fdisplay(fd,#Depth=2048); $fdisplay(fd,#Width=32); $fdisplay(fd,#AddrRadix=2); $fdisplay(fd,#DataRadix=3); $fdisplay(fd,#Data); for(i=0;i2048;i=i+1) $fdisplay(fd,%2h%2h%2h%2h,rom[4*i+3],rom[4*i+2],rom[4*i+1],rom[4*i]); $fclose(fd); end wire rom_en; wire [31:0] rom_addr; reg [31:0] rom_data; always @ (posedge clk) if (rom_en) rom_data = #`DEL {rom[rom_addr+3],rom[rom_addr+2],rom[rom_addr+1],rom[rom_addr]}; else; wire ram_cen; wire ram_wen; wire [3:0] ram_flag; wire [31:0] ram_addr; wire [31:0] ram_wdata; reg [31:0] ram [511:0]; reg [31:0] ram_rdata; always @ (posedge clk ) if ( ram_cen ~ram_wen ) if (ram_addr==32he0000000) ram_rdata = #`DEL 32h0; else if (ram_addr[31:28]==4h0) ram_rdata = #`DEL {rom[ram_addr+3],rom[ram_addr+2],rom[ram_addr+1],rom[ram_addr]}; else if (ram_addr[31:28]==4h4) ram_rdata = #`DEL ram[ram_addr[27:2]]; else; else; always @ (posedge clk ) if (ram_cen ram_wen (ram_addr[31:28]==4h4)) ram[ram_addr[27:2]] = #`DEL { (ram_flag[3] ? ram_wdata[31:24]:ram[ram_addr[27:2]][31:24]),(ram_flag[2] ? ram_wdata[23:16]:ram[ram_addr[27:2]][23:16]),(ram_flag[1] ? ram_wdata[15:8]:ram[ram_addr[27:2]][15:8]),(ram_flag[0] ? ram_wdata[7:0]:ram[ram_addr[27:2]][7:0])}; else; always @ (posedge clk) if (ram_cen ram_wen (ram_addr==32he0000004) ) $write(%s,ram_wdata[7:0]); else; reg irq=1b0; initial begin #100000 irq=1b1; #10 irq=1b0; end arm9_compatiable_code u_arm9( .clk ( clk ), .cpu_en (