Exploring P4 Trace Cache Features探索P4跟踪缓存功能.pptVIP

Exploring P4 Trace Cache Features Ed Carpenter Marsha Robinson Jana Wooten Problem Statement Explore characteristics of the P4 Trace Cache using microbenchmarks and performance counters related to branching and Trace Cache Approach Determine characteristics of the Pentium 4 processor that will help us evaluate the P4’s trace cache Using a performance monitoring tool (Intel’s Vtune Performance Analyzer) measure the data we need and analyze it to find limitations on the trace cache Some P4 Characteristics Like most high performance processors, the P4 has special on-chip hardware for performance monitoring. This hardware typically includes Event detectors and counters Qualification of event detections and counting by privilege mode and event characteristics Support for event-based sampling P4 characteristics cont. Common problems faces by modern processors Small number of counters Inability to distinguish between speculative and non-speculative events Imprecise event-based sampling With 42 million transistors (compared to 28 million of the P3), the P4 has overcome these problems 48 event detectors and 18 event counters Provides instruction-tagging to enable counting of nonspeculative performane events Provides support for imprecise event-based sampling (IEBS) and precise event-based sampling (PEBS) Trace Cache Special instruction cache for capturing long dynamic instruction sequences. Each line stores a snapshot, or trace, of the dynamic instruction stream P4 executes trace caches when there is an L1 cache hit (which is over 90% of the time) Characteristics of Trace Cache Stores instructions after they’ve already been decoded into μops (“micro-ops”). μops – RISC-style instructions Cache Line Size: 6 μops Trace Cache Size: 12K μops Branch Prediction hardware is used knows about any branch and fetch instructions that follow the branch. Conditional Branches can cause problems Won’t know if wrong until branch condition check in ALU0 Entering The Execution Pipelin