Activation Record Format：激活记录格式.pptVIP

CSS 372 Lecture 1 Simple ComputerData Paths Simple Input / Output Simple Memory Mapped I/O Simple Traps Execute TRAP “vector” - Operating System Service Routines 2) Trap Vectors are at memory locations [0000:00FF] Trap Vectors contain addresses of Trap Service Routines (PC) is loaded into R7 Address of Trap Service Routine loaded into PC Service Routine Program executed Trap service routine program ends with an RET ( (R7) loaded into PC) Simple ComputerData Paths Simple Memory Mapped I/O Interrupt Physical Model CPU Memory Device Interrupt Physical Model CPU General Purpose Registers PC Storage – R7 Stack Pointer R6 Program Status Word (PSW) – Includes State Program Priority Condition Codes (CC) User stack Pointer Storage – USP.saved Supervisor Stack Pointer Storage – SSP.saved Hardware to communicate over the BUS Memory User program Interrupt Service Routine Operating System Interrupt Vector Table Includes an entry that points to the Interrupt Service Routine (Interrupt vector #) Device Status/Control Register(s) – Includes: Interrupt Enable bit Interrupt bit (sometimes called ready or done) Priority Level for Interrupt Service Routine (In hardware or firmware) Interrupt vector number (In hardware or firmware) Hardware to communicate with CPU over the BUS Interrupt Sequence What does the programmer do? What does the computer do? Interrupt Sequence Programmer Action: Enable Interrupts by setting “intr enable” bit in Device Status Reg Enabling Mechanism for device: When device wants service, and its enable bit is set (The I/O device has the right to request service), and its priority is higher than the priority of the presently running program, and execution of an instruction is complete, then The processor initiates the interrupt Process to service the interrupt: The Processor saves the “state” of the program (has to be able to return) The Processor g