用于高速adc时钟系统的高性能锁相环研究-微电子学与固体电子学专业论文.docx

ABSTRACTthe unideal effects of CP have also been depressed efficiently, and the linearity of the VCO is good with the centre output frequency of 200MHz. The power dissipation of the whole circuits is 14.6mW when the power supply is 1.8V. In addition, the PLL is simulated under different process corners, temperatures and supply voltages. The simulation results show that it can operate well under all these PVT conditions.In the end, condisering the devices matching, the circuit symmetry and the protecting of sensitive blocks adequately, the PLL’s layout is drew using the Virtuosotools in the Cadence environment. It has a total area of 520μm×380μm.Keywords：Phase-Locked Loop, clock stabilizing, charge pump, voltage controlled oscillator, low jitter目录目录第一章 绪论 ·················································································································· 1 1.1 研究目的及意义 ····································································································· 11.2 技术发展和现状 ····································································································· 21.2.1 国内研究现状 ·································································································· 31.2.2 国外研究现状 ·································································································· 41.3 本文的组织结构 ····································································································· 6 第二章 锁相环的基本原理 ·························································································· 7 2.1 锁相环的应用 ········································································································· 72.1.1 频率合成 ·········································································································· 72.1.2 时钟产生和抑制时钟偏斜··············································································· 72.1.3 时钟数据恢复 ·········································································