双语课件（第9章） 9. Introduction to VHDL 《数字的设计基础（双语教学版）》Barry Wilknson .pptVIP

* 9. Introduction to VHDL 9.1 A simple example in VHDL 9.2 Stylistic issues 9.3 The IEEE library 9.4 Conditionals in VHDL 9.5 Handling multi-bit signals 9.1 A simple example in VHDL 1. Entity We will start off with a NAND gate. The first thing is to say what the device looks like to the outside world. This basically means describing its port map, i.e. the signals that flow in and out of it. 9.1 A simple example in VHDL To describe this in VHDL, we use an entity declaration. ENTITY nandgate IS PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC ); END; Each of the signals in the port map is declared as having a mode and a type. The mode can be IN or OUT, and simply says whether the signal is an input or an output. 9.1 A simple example in VHDL The type STD_LOGIC represents a signal that bit can a value of ‘0’, ‘1’, ‘X’ or ‘U’. STD_LOGIC is the normal way to describe logic signals that appear at the input or output of gates, or at wires in between them. ‘X’ means unknown ‘U’ means uninitialized, i.e. a signal that has not yet been assigned any valid logical value. 9.1 A simple example in VHDL If we want to check that our description is functioning correctly, we can feed it into a simulator, a program that predicts how the outputs would change in response to changes in the input. 9.1 A simple example in VHDL 3. BEGIN and END statements VHDL uses the keywords BEGIN and END to indicate the beginning and end of a block respectively. 4. Semicolons VHDL uses the semicolon to indicate the end of a statement. 9.2 Stylistic issues 1. Case VHDL is not case sensitive. 2. Spaces and indents Any number of spaces can be used between words without affecting the meaning of the code. 3. Returns Putting in a carriage return makes no difference to the function of the code. 9.2 Stylistic issues 4. Annotating END statements In a long description, in order to keep track, we can put the name of what we intend to end after the END statement. ENTITY