时序逻辑电路 西安交大数电实验时序逻辑电路实验报告.docVIP

时序逻辑电路 西安交大数电实验时序逻辑电路实验报告 实验名称：时序电路实验 一．实验目的： 1. 学习使用HDL进行时序电路设计； 2. 学习编辑顶层文件和用户约束文件； 3. 熟悉同步和异步的概念及实现方法； 4. 熟悉在Basys2开发板简单外围设备的控制； 5. 熟悉时钟的分频方法及占空比的调节。 二．预习内容 1. 用HDL设计一个秒脉冲（1s,2s,3s）发生器，并用LED显示： 分析：本电路设计主要分为三个部分：分频，计数，译码 1.1HDL源文件（Verilog）: module mod10( input clk, clr, output reg[6:0] a_to_g, output wire[3:0]an, output reg[3:0]q ); assign an = 4’b1110;//最右译码管使能 reg [26:0] counter;//时钟分频，默认时钟为50MHZ，分频为1HZ，即周期为1s always @ (posedge clk) if (counter == counter else counter reg clk_div;//引入新的电平 always @ (posedge clk ) if (counter == clk_div always @ (posedge clk_div or posedge clr) begin if(clr==1) q else if (q == 9) q else q end always @(*) case (q) 0:a_to_g = 7’b0000001; 1:a_to_g = 7’b1001111; 2:a_to_g = 7’b0010010; 3:a_to_g = 7’b0000110; 4:a_to_g = 7’b1001100; 5:a_to_g = 7’b0100100; 6:a_to_g = 7’b0100000; 7:a_to_g = 7’b0001111; 8:a_to_g = 7’b0000000; 9:a_to_g = 7’b0001100; default:a_to_g = 7’b0000001; endcase endmodule 1.2Basys2约束文件： NET “q[0]” LOC = “G1”; NET “a_to_g[0]” LOC = “M12”; NET “a_to_g[1]” LOC = “L13”; NET “a_to_g[2]” LOC = “P12”; NET “a_to_g[3]” LOC = “N11”; NET “a_to_g[4]” LOC = “N14”; NET “a_to_g[5]” LOC = “H12”; NET “a_to_g[6]” LOC = “L14”; NET “an[3]” LOC = “K14”; NET “an[2]” LOC = “M13”; NET “an[1]” LOC = “J12”; NET “an[0]” LOC = “F12”; NET “clk” LOC = “B8”; NET “clr” LOC = “G12”; 2.设计一个带有异步清零和置数信号（置数为全逻辑1）的4位寄存器，并在开发板上验证 2.1HDL源文件： module regf(clr,clk,d,load,q ); input wire clk; input wire clr; input wire load; input [3:0]d; output [3:0]q; reg [3:0] q; always @ (posedge clk or posedge clr) begin if (clr == 1) q else if (!clrload) q[0]q[1]q[2]q[3]end//同步置数 else q end endmodule 2.2约束文件： NET “clk” LOC = “B8”; NET “clr” LOC = “P11”; NET “load” LOC =“L3”; NET “q[3]” LOC = “G1”; NET “q[2]” LOC = “P4”; NET “q[1]” LOC = “N4”; NET “q[0]” LOC = “N5”; NET “d[3]” LOC = “G3”; NET “d[2]” LOC = “F3”; NET “d[1]” LOC = “E2”; NET “d[0]” LOC = “N3”; 2.3仿真文件： module regftest; // Inputs reg clr; reg clk; reg [3:0] d; reg load;