一种基于FPGA的新型全数字锁相环的建模 及分析.pdf

Journal of Electrical Engineering 电气工程, 2015, 3(4), 99-106 Published Online December 2015 in Hans. /journal/jee /10.12677/jee.2015.34013 Modeling and Analysis of a Novel All-Digital Phase-Locked Loop Based on FPGA Bin Yi, Feng Pan, Guoying Lin, Wei Zhao Electric Power Research Institute of Guangdong Power Grid Corporation, Guangzhou Guangdong th st th Received: Nov. 16 , 2015; accepted: Dec. 1 , 2015; published: Dec. 8 , 2015 Copyright © 2015 by authors and Hans Publishers Inc. This work is licensed under the Creative Commons Attribution International License (CC BY). /licenses/by/4.0/ Abstract This paper proposed a novel all-digital phase-locked loop (ADPLL). By using the self-sampling PI control method, it can obtain a phase-locked output signal without steady-state error and with less jitter. The designed ADPLL is able to adjust the mode number of the digital loop filter accord- ing to the phase error between the two input signals of the digital phase detector. In this way, the ADPLL can optimize the lock-in speed when the system stability is also guaranteed. The paper es- tablishes the mathematical model of the ADPLL based on the analysis of the operating characteris- tic of each module. Using the obtained system transfer function, the paper analyzes the perfor- mance parameters of the ADPLL, and provides the guiding principle of the parameters design. The validity of theoretical analysis is verified by experimental test in the final of this paper. Keywords All-Digital Phase-Locked Loop, PI Control, Mathematical Modeling, Parameter Analysis 一种基于FPGA的新型全数字锁相环的建模 与分析 易 斌，潘 峰，林国营，赵 伟 广东电网有限责任公司电力科学研究院，广东 广州 收稿日期：2015年11月16 日；录用日期：2015年12月1 日；发布