VMM验证平台中ISO14443通讯接口的参考模型建立-软件工程专业论文.docxVIP

摘要 摘要 随着数字集成电路规模越来越大，设计越来越复杂，验证的难度也随之增加， 设计新加一项功能，验证增加不止一条测试案例，实际项目中验证所占时间更是 高达整个项目研发周期的 70%，搭建高效的验证平台，开发优秀的验证环境，成 了当前集成电路设计工作的重要任务。 目前双界面卡的应用在国内乃至国际迅猛发展，已经证明了双界面卡应用的 美好前景。本文就双界面卡中符合 ISO/IEC14443 协议的非接触射频通讯接口模块 验证提出的一种更高效的验证方法，即在传统的基于 VMM 采用随机约束激励的 验证平台中，加入高抽象语言 SystemVerilog 搭建的参考模型，参考模型提供的黄 金响应使得对 DUT 功能正确性的判定变得更加简单高效，参考模型的加入也使得 注入错误的验证得以轻松实现，在验证平台中加入参考模型大幅提高了验证效率， 同时也提高了验证平台的可重用性能、可移植性，缩短了芯片研发周期。 本论文首先介绍阐述了 VMM 验证方法学，之后介绍 ISO/IEC14443 通讯协议 以及 DUT 的 RTL 设计规范，随后将传统验证平台与参考模型验证平台做出比较说 明。本论文中，重点工作是设计编写射频通讯接口的参考模型，论文中重点介绍 说明了参考模型设计方法以及代码结构，参考模型设计编写完成后，嵌入到传统 的验证环境中，进行前端 RTL 仿真，仿真结果表明，在传统验证环境中加入参考 模型能提高验证的覆盖率。 关键词：验证 VMM SystemVerilog 参考模型 Abstract Abstract With the increasing scale of digital integrated circuits, the design is more complicated, the difficulty of verification also increases. Adding a new feature needs more than one test case. In a real project, verification has taken up 70 % of the entire development cycle. How to build an efficient verification platform and develop a excellent verification environment has been priority in current integrated circuit design work. The application of dual interface card is increasing rapidly among world nowadays, which suggests a promising future of dual interface card application. In this article, for dual interface cards that meets ISO14443 protocol, we would provide a more efficient verification method for non-contact RF communication interface module, which is adding reference module built by high abstract language SystemVerilog based on traditional VMM random constraint incentive-based verification platform. Golden response provide by this reference model makes DUT functional check more simple and efficient. Also, it improves portability and reusability of verification platform and shortens the chip development cycle. This paper first described the VMM verification methodology, and after to introduce the ISO/IEC14443 communication protocol and the DUT RTL design specifications, followed by the traditional verification