Algorithms and Tools外文.pptVIP

* Basic Architecture CPU, pipelining Memory hierarchy, cache * Computer Performance CPU operates on data. If no data, CPU has to wait; performance degrades. typical workstation: 3.2GHz CPU, Memory 667MHz. Memory 5 times slower. Moore’s law: CPU speed doubles every 18 months Memory speed increases much much slower; Fast CPU requires sufficiently fast memory. Rule of thumb: Memory size in GB=R_theor in GFLOPS 1CPU cycle (1 FLOPS) handles 1 byte of data 1MFLOPS needs 1MB of data/memory 1GFLOPS needs 1GB of data/memory Many “tricks” designed for performance improvement targets the memory * CPU Performance Computer time is measured in terms of CPU cycles Minimum time to execute 1 instruction is 1 CPU cycle Time to execute a given program: n_c: total number of CPU cycles n_i: total number of instructions CPI = n_c/n_i, average cycles per instruction t_c: cycle time, 1GHz ? t_c=1/(10^9Hz) = 10^(-9)sec = 1ns * To Make a Program/Computer Faster… Reduce cycle time t_c: Increase clock frequency; however, there is a physical limit In 1ns, light travels 30cm Currently ~ GHz; 3GHz cpu ? light travels 10cm within 1 cpu cycle ? length/size must be 10cm. 1 atom about 0.2 nm; Reduce number of instructions n_i: More efficient algorithms Better compilers Reduce CPI -- The key is parallelism. Instruction-level parallelism. Pipelining technology Internal parallelism, multiple functional units; superscalar processors; multi-core processors External parallelism, multiple CPUs, parallel machine * Processor Types Vector processor; Cray X1/T90; NEC SX#; Japan Earth Simulator; Early Cray machines; Japan Life Simulator (hybrid) Scalar processor CISC: Complex Instruction Set Computer Intel 80x86 (IA32) RISC: Reduced Instruction Set Computer Sun SPARC, IBM Power #, SGI MIPS VLIW: Very Long Instruction Word; Explicitly parallel instruction computing (EPIC); Probably dying Intel IA64 (Itanium) * CISC Processor CISC Complex instructions; Large number of instructions; Can complete more complica