Direct digital synthesis enables digital PLLs理工类毕业设计英文文献翻译.docVIP

学士学位论文 附录二 附录二 文献翻译 Direct digital synthesis enables digital PLLs Direct digital synthesis, together with a DAC and a high-performance digital phase detector, overcome several fundamental drawbacks in analog PLLs, such as asymmetry in the phase detector or bandwidth limitations and phase noise in the VCO. Furthermore, because the circuitry is digital, feedback-loop parameters are adjusted by changing numerical coef?cients in device registers rather than changing electrical parameters in physical components, the latter process being especially dif?cult for ASIC designs. the performance of analog PLLs has steadily improved, with operating frequencies extending up to 8 GHz and beyond. Industry mainstays for many years, these PLLs are well understood, and offer inexpensive solutions for frequency synthesis and jitter clean up. Recently, digital PLLs based on direct digital synthesis (DDS), have emerged as attractive alternatives in certain applications. This article explores the differences between analog PLLs and DDS-based digital PLLs, and how these differences can be used to guide the designer toward the best option. A digital PLL implements traditional PLL building blocks using digital logic. While there are many ways to implement a digital PLL, this article will focus on DDS-based digital PLL architectures. So as to a typical analog PLL, The reference divider, which is the ?rst block encountered by an incoming signal, is no different from that of an analog PLL. The reference divider reduces the frequency of the incoming signal before it goes to the phase detector. The reference divider setting plays a key role in PLL behavior. If the designer must use a large reference divider and a low phase-detector frequency to generate the desired output, the maximum loop bandwidth will be constrained. The digital phase detector In an analog PLL, the phase detector generates charge-pump current pulses, whose duration is proportional to t