嵌入式系统 read.pptx

第二大部分 S3C2410微处理器暨接口PART I S3C2410处理器 －overviewS3C2410处理器性质－architectureIntegrated system for hand-held devices and general embedded applications16/32-Bit RISC architecture and powerfull instruction set with ARM920T CPU coreEnhanced ARM architecture MMU to support WinCE, EPOC 32 and LinuxInstruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performanceARM920T CPU core supports the ARM debug architecture.Internal Advanced Microcontroller Bus Architecture (AMBA) (AMBA2.0, AHB/APBS3C2410处理器性质－System ManagerLittle/Big Endian supportAddress space: 128M bytes for each bank (total1G bytes)Supports programmable 8/16/32-bit data bus width for each bankFixed bank start address from bank 0 to bank 6Programmable bank start address and bank size for bank 7Eight memory banks:– Six memory banks for ROM, SRAM, and others.– Two memory banks for ROM/SRAM/Synchronous DRAMSupports various types of ROM for booting(NOR/NAND Flash, EEPROM, and others) S3C2410处理器性质 －NAND Flash Boot LoaderSupports booting from NAND flash memory4KB internal buffer for bootingSupports storage memory for NAND flash memory after booting S3C2410处理器性质 －Cache Memory64-way set-associative cache with I-Cache (16KB) and D-Cache (16KB)8words length per line with one valid bit and two dirty bits per linePseudo random or round robin replacement algorithmWrite-through or write-back cache operation toupdate the main memoryThe write buffer can hold 16 words of data and four addresses. S3C2410处理器性质 －Clock Power ManageThe clock power management block consists of three parts: clock control, USB control, and power control.Clock can be fed selectively to each function block by software.Power mode: Normal, Slow, Idle, and Power-off mode；Normal mode: Normal operating mode；Slow mode: Low frequency clock without PLL；Idle mode: The clock for only CPU is stopped.；Power-off mode: The Core power including all peripherals is shut down.Woken up by EINT[15: