高级体系结构课程要点研课程要点与复习课件.ppt

高级体系结构课程要点 第一章 前言 计算机技术快速法进步的原因 技术进步－－Moore定律发展 体系结构发展 体系结构演化过程 现代计算机体系结构的组成 高级计算机体系结构研究范畴 计算机系统结构的分类 Flynn分类法---定性 冯氏分类法---定量 第三章　Instruction-Level Parallelism and Its Dynamic Exploitation What is pipelining? How is the pipelining Implemented? What makes pipelining hard to implement? How does CPI descend ? CPI=1 CPI1 CPI1 Ideal Performance for Pipelining Ideal speedup equal to Number of pipe stages MIPS instruction format Works in the MIPS 5 stage pipeline The MIPS pipelining Pipeline hazard: the major hurdle Structural hazards Data hazards Control hazards be resolved by Stall Solution imaginable for Structural hazards “ double bump” Insert stall provide another memory port split instruction memory and data memory use instruction buffer fully pipelined function unit Why allow machine with structural hazard ? Solution imaginable for Data hazards Interlock: insert stalls Detect: Data Hazard Logic Forwarding: reduce data hazard stalls compiler to avoid load stall Solution imaginable for Control hazards Move the Branch Computation Forward Simple solutions Freeze or flush the pipeline Predict-not-taken (Predict-untaken) Treat every branch as not taken Predict-taken Treat every branch as taken Delayed branch a,b,c Cancelling function Extending the MIPS Pipeline to Handle complex pipeline structure Pipelining time parameter Latency Initiation interval The out of order The new types of data hazards RAW Stalls arising WAW Instruction-Level Parallelism CPIpipelined = Ideal pipeline CPI+ pipelined stall cycles per instruction =1+ Structual stalls + RAW stalls + WAR stalls + WAW stalls + Control stalls Basic Block ILP is quite small Data Dependence and Hazards True Data Dependence→ RAW( Read after write) Name dependence Anti-dependence → WAR( Write after read) Output dependence → WAW(Write after write) Some Property about Dependences are a property of programs hazard or length of any stall is a property of the pipeline (hardware) Control Dependencies Bra