版7-14_Superscalar.pptVIP

William Stallings Computer Organization and Architecture7th Edition Chapter 14 Instruction Level Parallelism and Superscalar Processors Chapter 14Instruction Level Parallelism and Superscalar Processors Key Terms（1） Antidependency Branch prediction Commit (托收，提交） Flow dependency In-order issue In-order completion Instruction-level parallelism Instruction window Machine parallelism Micro-operations Micro-ops Chapter 14Instruction Level Parallelism and Superscalar Processors Key Terms（2） Out-of-order completion Out-of-order issue Output dependency Procedural dependency Read-write dependency Register renaming Resource conflict Retire（回收） Superpipelined Superscalar True data dependency Write-read dependency Write-write dependency What is Superscalar? Common instructions (arithmetic, load/store, conditional branch) can be initiated and executed independently Equally applicable to RISC CISC In practice usually RISC initiated vt.开始，发起；传授；创始， independent 独立的,自治的,自主的,单独的,分开的 Why Superscalar? Most operations are on scalar quantities (see RISC notes) Improve these operations to get an overall improvement General Superscalar Organization Superpipelined Many pipeline stages need less than half a clock cycle Double internal clock speed gets two tasks per external clock cycle Superscalar allows parallel fetch execute Superscalar vSuperpipeline Limitations Instruction level parallelism (ILP1) Compiler based optimisation Hardware techniques Limited by True data dependency （真实数据相关性） Procedural dependency （过程相关性） Resource conflicts （资源冲突） Output dependency （输出相关性） Antidependency （反相关性） True Data Dependency （W-R) ADD r1, r2 (r1 := r1+r2;) MOVE r3,r1 (r3 := r1;) Can fetch and decode second instruction in parallel with first Can NOT execute second instruction until first is finished Procedural Dependency Can not execute instructions after a branch in parallel with instructions before a branch Also, if instruction length is not fixed, instructions have to be decoded to