版8-16_Control Unit.pptVIP

William Stallings Computer Organization and Architecture8th Edition Chapter 16 Control Unit Operation Key Terms Control bus Control path Control signal Control unit Hardwired implementation Microoperations Control unit operation Micro-Operations A computer executes a program Fetch/execute cycle Each cycle has a number of steps see pipelining Called micro-operations Each step does very little Atomic operation of CPU Constituent Elements of Program Execution Instruction Cycle with Indirect Fetch - 4 Registers Memory Address Register (MAR) Connected to address bus Specifies address for read or write op Memory Buffer Register (MBR) Connected to data bus Holds data to write or last data read Program Counter (PC) Holds address of next instruction to be fetched Instruction Register (IR) Holds last instruction fetched Fetch Sequence Address of next instruction is in PC Address (MAR) is placed on address bus Control unit issues READ command Result (data from memory) appears on data bus Data from data bus copied into MBR PC incremented by 1 (in parallel with data fetch from memory) Data (instruction) moved from MBR to IR MBR is now free for further data fetches Data Flow (Fetch Diagram) Fetch Sequence (symbolic) t1: MAR - (PC) t2: MBR - (memory) PC - (PC) +1 t3: IR - (MBR) (tx = time unit/clock cycle) or t1: MAR - (PC) t2: MBR - (memory) t3: PC - (PC) +1 IR - (MBR) Rules for Clock Cycle Grouping Proper sequence must be followed MAR - (PC) must precede MBR - (memory) Conflicts must be avoided Must not read write same register at same time MBR - (memory) IR - (MBR) must not be in same cycle Also: PC - (PC) +1 involves addition Use ALU May need additional micro-operations Data Flow (Indirect Diagram) Indirect Cycle MAR - (IRaddress) - address field of IR MBR - (memory) IRaddress - (MBRaddress) MBR contains an address IR is now in same state as if direct addressing had been used (What does this say about IR size?) Data Flow (Indirect Diagram) t1: MAR - (P