基于SoC的边界扫描测试硬件系统的设计-计算机应用技术专业论文.docxVIP

江苏太学硕士学位论文摘 江苏太学硕士学位论文 摘 要 边界扫描测试技术是一种可测性设计技术，W用于实现芯片级、扳级甚至系 统级的电路测试和故障诊断。随着集成电路设计和制造工艺的不断进步，边界扫 揍溅试鼓零歪褥至l越来越多熬关注。毽枣子嚣毒蕃溪内藏芝标准豹瓣试平套，剩震 边界扫描测试机制进行电路测试和诊断还较为少见。 零文在分橱边器扫接溯试援零豹基本承理及IEEEll49．1标准沟基稻t，提 出并讨论了一种基于SoC的边界扫描测试硬件系统的设计方案。根据设计流程， 首先将逸界扫描溅试硬件系统划分成边界扫描主控器、通信控制模块和测试存储 嚣模块三个部分，其中边界扫描主控器是该系统的核心部分，又可以缨分必CPU 和边界扫描接口两个模块。然后利用QuartuslI软件对各模块进杼设计、综合、 傍囊，最藤下载到FPGA蕊片孛遴霉谖试。谚试终栗表明，该溅试疆锌系统产生 的测试信号完全满足IEEEll49．1标准的时序要求，可用于集成电路和印制电路 叛瓣透赛织箍嚣试。 本课题利用Altera公闭的Nios开发扳作为硬件开发平台，借助Qua_．_rtuslI软 件进行设许，完成了一个边秀扫描硬件溺试系统的设计。本文主豢利用SoC设 计方法学来实现边界扫描测试硬l牛系统的设计。课题选用Altera公司鲍 EPISl0F780C6ES芯片来蜜现最终的边界扫描测试硬件系统，完成一个可编程单 蕊冀系绕黥设诗。 本课题的研究表明，将边界扫描测试硬件系统做成一个基于m核SoC是完 全霹行戆，霹滚滚建透雾摆搓溅试硬箨系绞蠡孽快逮、寿效、参受豹发震趋势。 关键锈；FPGA，VHDL，边赛摇摇主控嚣，p狻，SoC，Nios。边界扫播溅试 江苏大学硕士学位论文Abstract 江苏大学硕士学位论文 Abstract As a Design—for-Testability technique，Boundary-scan testing technology is mostly applied to chip-level，board-level or system-level circuit testing and defaults diagnosis．Wjtll the increasing development ofIC design and manufacturing technique． boundary-scan technique is attracting more and more interest．In China,however,the absence of standard testing platform results in the rare application of boundary scan testing technology to circuit testing and defaults diagnosis． 仳article analyzes the basic principle of boundary-scan testing technology and theIEEEll49．I Standard，andputsforwardadesign solutionofboundary·scantesting hardware system based on SoC．According to the design procedure，the system is divided into three parts，which are the boundary-scan master module，the communication controlling module and the testing memory module．The first one of the three modules is the gore of the whole system and subdivided into the CPU module and the boundary scan interface module．After each module has been designed,synthesized and emulated by using QuartusII，the boundary SCan testing hardware system is downloaded into FPGA to be debugged．ne debugging and testing results show that the testing signals produced by the system fully meet the time