高速数字电路的信号完整性分析.pdfVIP

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  • 2018-12-28 发布于广东
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3.Tosolvethe in establishesthesimulation circuit,it timingproblemshigh—speed in effectivedevice modifiesthe through model(IBIS platformHyperlynx model).It set-up timeandtheholdtime devicedata the oftheclock handbook,SO by outputdelay provided onthe DSPand canbe of determined.Moreowr,basedrequirements SDRAM, signal timing meetthe constraintconditionsofthePCB should designs wiring Canuseour rulersto theirboard. engineers proposeddesign 4.Tosolvethe ofthe article a circuit,the powerintegrityproblemshigh—speed proposes methodof resonantofPDN branchloss.It throughincreasing inhibitingparallel decoupling introducesaseriesresistanceintothe branchtomakePDNloss decoupling increase,which PDN resonant.Thetheoreticalmodelis and suppressesparallel providedsupportedby simulation on PIsoftware.Theresultsshow factorof Hyperlynx that,thequality experiment Q PDNat resonantwillbeinhibitedfrom282to13 a0.45 parallel throughintroducing into branch.Thisals

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