基于IP核的SoC测试结构多目标优化技术研究-测试计量技术及仪器专业论文.docxVIP

摘 要 当今，系统芯片(System on Chip,SoC)已成为集成电路设计的一大主流，基于 IP 核复用的 SoC 设计方法可以加快产品上市时间。但是由 IP 核集成的系统芯片 SoC 的测试也成为了芯片制造过程中的一大挑战。 本文针对 SoC 测试结构多目标联合优化问题开展研究。在研究了 IEEE 1500 标准的基础上，重点对 IP (Intellectual Property)核的测试壳 Wrapper 结构及芯片级的 测试控制器进行了研究。在此基础上，研究配置有测试壳 Wrapper 结构的 IP 核的 测试时间和测试功耗，包括以减少 IP 核测试时间为目的的 IP 核内部扫描链的平衡 化和测试壳 Wrapper 输入输出单元的平衡分配，以及建立 IP 核的测试功耗研究模型。 针对 SoC 的测试时间与测试功耗相互制约的关系，建立了一个新颖的基于 TAM(Test Access Mechanism)分组策略的测试时间与测试功耗多目标优化模型，在深入研究多目 标遗传算法的基础上，将其应用于优化模型的求解。并将模型的优化结果创新性地应 用于 SoC 测试结构的研究，并进行了基于 TAM 分组优化的 SoC 测试结构设计。 最后采用 ITC’02 标准电路中的 h953 、d695 和 p93791 进行多目标遗传算法 和联合优化模型的验证，另外设计了一个被测电路对所设计的基于 TAM 分组策略的 SoC 测试结构进行了验证。结果表明，算法能够获得模型的较好解，设计的测试结构 能够实现算法的优化结果，体现了模型及测试结构的有效性和实用性。 关键词：SoC；IP 核；多目标优化；测试结构；TAM I Abstract At present, System-on-Chip (SoC) has become a mainstream of Integrated Circuit (IC) design. The method of SoC design, which is based on Intellectual Property (IP) core reuse, can speed up the time to market. However, the test of SoC integrated by IP cores has become a major challenge in the chip manufacturing process. The problem about multi-objective joint optimization of SoC test structure was studied. Based on the IEEE 1500 standard, the Wrapper structure of IP core and the chip-level test controller were mainly researched on. On the basis of them, the test time and test power consumption of IP core were studied, which was covered with the Wrapper, including the balance of the internal scan chains in IP cores for the purpose of reducing IP core test time, the allocation of Wrapper input and output units, and the establishment of test power research model based on IP core. Aiming at mutual checks between SoC test time and test power consumption, a novel model was established , which was based on TAM grouping strategy about the Multi-objective optimization of test time and test power consumption. At the same time, the multi-objective genetic algorithm was studied and applied it to the solution of the optimization model. In the paper, the optimization res