基于IP软核复用技术的多处理器片上系统研究-计算机应用技术专业论文.docxVIP

桂林工学院硕士学位论文ABSTRACT 桂林工学院硕士学位论文 ABSTRACT Multi·processor SOC is in keeping with the trend of the embedded system design，and the FPGA device manufacturers，the open·source organizations，with the third party chip design companies have already developped a large mount of verified well·worked soft IP cores including CPU cores，thus，this thesis using the method of reusing soft IP cores to construct a multi-processor system running on FPGA．，and it solves the communication problems and CACHE coherence problems under the condition of non-changing original IP soft core’s inner logics． After briefly introduced the FPGA devices，IP core reusing technology,SOPC technology and four usually．used CPU soft cores，this article describes the primary structure of multi·processor on programmable chip based on IP cores reusing，it’S developing flow and it’S operating system importing． The solutions for communication problems in multi-processor system on chip when reusing IP cores including the decision·making of choosing communication IP cores and the topology structures of multi-processors were also provided in this article．It using Nios II multi-core systems to exemplify the solution of the cache coherence problem in the case of that the Cache logic couldn’t be changed within the reused CPU soft cores． Due to the light．weight CPU soft COGS have no MMU，while the full-function ones have， this arti毛build each multi．processor system platform for both Nios II cores(which are light—weight cores)and OpenRISC 1200 cores(which are full·function cores)with the detail implemental steps，in addition to an elemental simulation for verifying the bus interface unit’S function in OpenRISC 1200 core based multi·processor system platform． This article also provided an application instance of solution tO the reusing IP cores’ multi．processor system：It constructs a B／S systems running on FPGA based on SOPC multi．processon It describe the architecting methods and developing ways tO construct an IP reusing multi