《基于FPGA的交通灯控制器》.docVIP

《基于FPGA的交通灯控制器》 课程设计 学生姓名： 刘阳升 学 号： 200656220330 专业班级： 电子信息科学与技术06-03班 指导教师： 贺慧勇 二○○八 年 十二月 二十五日 摘要 Verilog HDL作为一种规范的硬件描述语言,被广泛应用于电路的设计中。利用Verilog的设计描述可被不同的工具（包括验证仿真、时序分析、测试分析以及综合）所支持,可用不同器件来实现。而可编程器件的广泛应用，为数字系统的设计带来了极大的灵活性。由于可编程器件可以通过软件编程对硬件的结构和工作方式进行重构，使得硬件的设计可以如同软件设计那样快捷方便。 本文用Verilog HDL设计了一个交通灯控制系统，主干道交通灯按绿－黄－红变化，支干道交通灯按红－绿－黄变化。设计采用了自顶向下的设计方法，首先根据功能将电路分为div(包括div1和div2)、counter、controller、Fenwei(包括Fenwei1和Fenwei2)、demx模块，然后针对每个模块进行开发。利用QuartusII6.0中的仿真工具对每个模块进行仿真，保证功能正确。在此基础上，将所有模块连接起来，形成完整的设计，并用QuartusII6.0中的仿真工具再次仿真。仿真结果表明功能正确，符合设计要求。最后利用QuartusII6.0将程序下载到Altera FPGA芯片EP1C3T144C8中，实际结果表明电路工作正常，满足了设计要求。 【关键词】 Verilog HDL，交通灯，FPGA 【Abstract】 Verilog HDL is a widely used hardware description language in IC design field. It is supported by different EDA tools of simulation, succession analysis, synthesis, timing analysis and test analysis. Designs with Verilog HDL can be easily implemented in different devices, for example, programmable logic devices. The programmable devices are widely used in digital system design nowadays and they bring great flexibility to the engineer. The programmable devices can be programmed by software, making the hardware design as easy as software design. This paper reports a traffic light controller system design using the Verilog HDL.The Main-Artery traffic lights change in the order of green-yellow- red and the Branch-Artery traffic lights change in the order of red -green-yellow. Top-down design method is applied in this design. The system is divided into 5 sub-blocks: div(including div and div2), counter, controller,Fenwei(including Fenwei1 and Fenwei2) and demx. Each block is well designed and simulated in QuartusII6.0 to goatee the function is right. The sub-blocks are then connected to build the whole system. The whole system is simulated again in QuartusII6.0 and tested to be right. By compiling in Quartus6.0, the design is p