超大规模集成电路时钟线网的布线与优化算法-研究.doc

上海交通大学硕士学位论文 VLSI CLOCK TREE ROUTING AND OPTIMIZATION ALGORITHMS ABSTRACT With the VLSI fabrication process moving into very deep sub-micron technology, clock signal and the distribution of clock net have become one of key factors determining IC speed and caught relevant researchers’ eyes. For a synchronous VLSI system, two factors mostly affect the speed of circuit: one is the delay of the longest path in the combinational logic circuit, and the other is the biggest clock skew in the synchronous components. In the deep sub-micron technology, the switching speed of the combinational logic circuit has been improved enormously, so circuit performance is restricted by the clock skew. The excessive clock skew not only leads to low performance but also results in the invalidation of synchronous control and the disorder of circuit function. Therefore the designer must solve the distribution of clock net by well-regulated routing in order to make sure of zero-skew or bounded skew. The first chapter introduces the design flow and VLSI CAD 3 上海交通大学硕士学位论文 technology in each design process. Subsequently the research significance of clock routing is discussed. Finally the organization of this thesis and innovative work are pointed out. In the second chapter the lately research development of the clock tree routing algorithms is enumerated in detail, including abstract topology generation algorithm and planar merge embedding of topology algorithm. And two optimization techniques are briefly introduced: the buffer insertion technique and wire sizing technique. The third chapter makes a study on the delay model of interconnects. Some kinds of delay models in recent research are introduced: lumped RC delay model, distributed RC delay model, Elmore delay model and RLC delay model. Based on the Elmore delay for tree-like clock net, the more accurate RLC delay model for tree-like clock net is educed. It transforms tree-like interconnects into single interconnects for delay analysis. I