分片式处理器体系结构上的超块优化技术计算机系统结构专业论文.docxVIP

AbstractAbstract Abstract Abstract In the last decade，the overall performance of microprocessors has been improving at the rate of 50—60％each year．However,as the feature size of chip fabrication shrinks and approaches the size of a silicon atom，microprocessor academia and industry face many problems，such as the increasing power consumption of processors leading to the fast increase of heat dissemination and wire delay surging resulting in that the functional units electronic signal can reach in each cycle decrease rapidly and SO on．The two major sources of performance improvement， increasing clock rates and IPC，encounter huge challenges and lose their momentum． Traditional processor architectures can not accommodate new fabrication technology any more．Many research teams have come up with new processor architectures to substitute for traditional processor architectures，such as tiled processor architectures and SO on．At the same time，new tiled processor architectures require new compiling technology．The combination of hyperblock formation and optimization techniques with tiled processor architecture becomes a worthy research field． This thesis does research in the strengthes and potential of ti led processor architecture，its combination with hyperblock execution model and the direct communication among instructions in hyperblocks．This thesis also．introduces profile information and critical path length based software fanout tree generation algorithm and basic block characteristics based MOV instruction reduction hueristic algorithm， carries out theoretical analysis，implements the algorithms on TRIPS compi ler and scheduler and test the practical performance of them．Profi le information and critical path length based fanout tree generation algorithm makes use of profile information of programs and static characteristics of basic blocks，modifies Huffman coding algorithm and creatively applies it to software fanout tree generation problem．This algorithm can opt