virtex系列fpga内部互连线测试微电子学与固体电子学专业论文.docxVIP

摘要摘要 摘要 摘要 伴随着微电子工艺技术的飞速发展和集成电路规模的不断提高，现场可编程 门阵列(FPGA)器件的功能更强，复杂度进一步提高，而计算机辅助工具的不断 更新使得FPGA器件的设计周期缩短，但却使测试难度增大了，进而导致测试费 用和测试时间的增加。如今测试费用达到总开发成本的40％左右。如何有效的对 FPGA器件进行测试不但关系到FPGA器件产品的质量，而且关系到产品的设计周 期和开发成本等，所以，测试环节已经成为FPGA器件设计和开发中重要的一环。 而寻找测试路径是FPGA器件内部互连线测试最初、但却是最为重要和关键的一 步。为了在测试中减少测试工作量，提高测试效率，同时又能保证一定的测试覆 盖率，论文提出了一种可以在短时间内找到内部互连线的测试路径并且达到95％ 以上覆盖率的测试方法。该方法利用数组来表示测试路径节点，结合最大流算法 来寻找测试路径。论文对最大流算法的原理和流程进行了详细阐述，并通过编写 程序将提出的算法程序化、实用化，解决了FPGA测试中寻找测试路径的问题。 关键词：FPGA最大流算法互连线测试 AbstractAbstract Abstract Abstract The function of FPGAs is becoming increasingly stronger and the complexity has been increasing along with the development of microelectronics technology at very fast speed and the scale of integrated circuit has been enlarged endlessly．Further more，the design period of FPGA devices has been shrunk by the designer who uses the CAD tools，but the difficulty has been increased．n leads to the increase in time and expense spent on the testing．The expense spent on the testing is about 40 percent of the total ，cost．The testing of FPGAs impacts not only the quality of FPGA devices，but also the design period and cost．The problem of finding the testing path is the first step as well as the most important step of interconnects testing．In order to reduce the workload and enhance the efficiency of testing with the precondition of enough testing coverage of FPGA interconnects，this paper presents a testing method by which the testing path is easy to find and the testing coverage achieved is more than 95 percent．In this method, the nodes on the testing path are set in an array and the Max—flow algorithm is used to find the testing path．This Paper describes the principle and flow of the Max—Flow algorithm in detail．And then the proposed method is carried out by program．Thus，the problem of finding the testing path is solved． Keyword：FPGA Max-flow Algorithm Interconnects Test 西安电子科技大学 西安电子科技大学 学位论文独创性(或创新性)声明 秉承学校严谨的学分和优良的科学道德，本人声明所呈交的论文是我个人在 导师指导下进行的研究工作及取得的研究成果。尽我所知，除了文中特别加以标 注和致谢中所