基于功耗和噪声优化的12位流水线ADC系统级设计及建模-微电子学与固体电子学专业论文.docxVIP

IV IV System Design and Modeling for 12bit Pipelined ADC Based On The Optimization of Power and Noise ABSTRACT With the development of video equipment, it had required more and higher abilities of video ADC, and ADC is the core of video ADC. Pipelined structure is often used in the ADC of video ADC as pipelined ADC can achieve a good compromise between speed, accuracy, and power consumption performance. With the continuous improvement of the performance of the pipelined ADC, the complexity of circuit is also increasing. As system -level design and modeling can shorten the design cycle, increasing design reliability, it has gradually become an essential step in analog integrated circuit design. How to optimize power consumption，noise, and other non-ideal factors of pipelined ADC reasonably in system-level design and modeling, and thus provide theoretical guidance for circuit design is the key to the current system -level design of complex analog integrated circuits. This thesis firstly gives a brief description of 12 -bit pipelined ADC application background the video ADC and its main working principle, to determine the basic performance indicators of the modeling pipe lined ADC. And then the the main structure and working principle of the key modules were analysed, such as sample-and-hold circuits, MDAC circuit, Sub-ADC circuits and digital delay correction circuit. Based on these analyzes, the sample-and-hold module structure was initially identified. Then non-ideal factors of 12-bit pipelined ADC (such as noise, power consumption, offset and distortion) was analysed. Two preferred system architecture of project one (2.5 +1.5 × 7 +3) and project four (3.5 +1.5 × 6 +3) was choosed based on non-ideality factor, power consumption and chip area compromise. Finally, the ideal model and the non -ideal factors of 12-bit pipelined ADC key modules was system-level designed and modeled, r