0.13微米逻辑电路负偏压温度不稳定性的改善.pdf

0.13UM LOGIC NEGATIVE BIAS TEMPERATURE INSTABILITY IMPROVEMENT ABSTRACT With the semiconductor manufacture technology developed to deep-submicron technology, we need to face some new barriers and challenges. NBTI （Negative Bias Temperature Instability ） is one of the reliability issues we need to face. Because almost all the process steps can influence it, the improvement of 0.13um logic circuit NBTI performance is a challenge. Now, there is a company inbound that the NBTI lifetime of 0.13um logic circuit is only 1.5 years and need to be improved to above 10 years. Through the analysis of NBTI generation mode, we find that NBTI is major induced by Q (Interface trap charge)and Q (Fix charge) in gate oxide layer. it f Then we analyze all kinds of impact factors of NBTI and find the factors that can be improved. It includes: Silicon surface treatment before gate oxidation; nitrogen content in the gate oxide; fluorine content in the gate oxide; the prevention and cure of plasma induced damage. Combining the impact factors and 0.13um logic process, we decided the process steps that need to be improved. Front-end process include: sacrificed oxide remove process; gate oxide grows process; source and drain implantation process; hydrogen anneal process. Back-end process include: FSG(Fluorine Silicon Glass) deposition process; interconnect trench dry etch process and alloy process. We did 2 lots wafers split experiment at the related step. The experiment result shows: through adding the sacrificed oxide , over etch rate will induce low yield, and make the NBTI performance get wors