射频CMOS电荷泵锁相环的分析与设计-电路与系统专业论文.docx

ABSTRACT ABSTRACT PAGE PAGE IV ABSTRACT As one of the most important building blocks in radio-frequency transceivers, charge pump phase lock loop(CPPLL) provides steady local oscillate signal for mixer. The phase noise of CPPLL will influence the sensitivity of radio-frequency transceivers. Therefore, the low phase noise design is a huge challenge in PLL research. According to the DVB-C specification, we designed the CPPLL in DTV tuner based on Chartered 0.35um RF-CMOS process. We have chosen each block circuit structure in PLL and optimized them. The design of PLL was systemic researched, some nonideal phenomena in these circuits were analyzed and the corresponding eliminated methods were presented. Firstly, the systematic structure of CPPLL in DTV tuner was presented. Because the influence to PLL performance of the loop filter is greatly, such as phase margin, pull-up band and locking time, we need design the loop filter in advance. There are some differences in the loop filter, so the transform function was re-derived. The influence of filter parameters variation to the PLL responding was discussed, and we got the optimized approach of filter parameters variation which can keep PLL steady responding. Then, the relationship between locking time and PLL parameters was deeply discussed. We presented a new method to calculate the locking time in the DTV tuner PLL. The formulation of locking time was derived which can easily describe the relation locking time and PLL parameters. The CPPLL systematic simulation was implement by ADMS which is the analog digital mixed circuit simulation tool of Mentor Graphics. The locking time through simulation is agreed with the result of calculation. Secondly, the parameters and basic principle of LC oscillator were analyzed, and the influence of the MOS parasitical parameters to oscillator was considered. We summarize the VCO design approach, and the complementary cross coupled LC VCO is chosen, the MOS size and the resonance n