ASIC设计中时钟偏移分析.docxVIP

Analysis of Clock Skew in ASIC design Cao Haitao, Zheng Jianhong (Institute for RD of the 3th Generation Mobile Telecommunication Technology of Chongqing Chongyou Information Technology Co.Led, Chongqing 400065, P.R.China ) Abstract: Clock skew becomes more and more important to synchronization circuits in current ASIC design, and it is an increasing concern for high-speed circuit designers. Therefor, it has been a tough challenge to reduce defect of clock skew in designs. In this paper, firstly the generation principle of clock skew is analyzed. and then for solving its disadvantage we propos