(内存基本知识)DRAM工作原理.PPT

DRAM 1T-1C structure RAS: row address strobe CAS: column address strobe WE: write enable Address: code to select memory cell location DQ (I/O): bidirectional channel to transfer and receive data DRAM cell: storage element to store binary data bit Refresh: the action to keep data from leakage Active: sense data from DRAM cell Pre charge: standby state DRAM Key word DRAM cell array consist of so many cells. One transistor One capacitor Small sense amplifier Low input gain from charge sharing ?? CS : Small storage capacitor: 25fF CBL : Large parasitic capacitor: over 100fF Vc: Storage voltage VC