Synthesis Optimization - 综合优化,来自synopsys.pdfVIP

Synthesis Optimization Timing Optimizations Settings Use realistic design constraints, about 10 - 15% of the real goal. Over constraining your design can be counter- productive. Use clock, false path, and multicycle path constraints to make the constraints realistic. Select a balanced fanout constraint. A large constraint creates nets with large fanouts, and a low fanout constraint results in replicated logic. If the critical path goes through arithmetic components, try disabling Resource Sharing. You can get faster Times at the expense of increased area, but use this technique carefully. If the PR and synthesis tools report different critical paths, use a timing constraint with the -route option. For FSMs, use the onehot encoding style, because it is often the fastest implementation. If a large output decoder follows an FSM, gray or sequential encoding could be faster. For designs with black boxes, characterize the timing models accurately, using the syn_tpd, syn_tco, and syn_tso directives. Make sure that you pass your timing constraints to the place-and-route tools, so that they can use the constraints to optimize timing. 2 Re-timing FSM Compiler FSM Explorer Shannon Expansion Operand Reordering Setting Fanout Limits Route Constraint 3 Re-timing What is Re-timing Automatically moving registers across combinatorial logic to improve timing while ensuring identical logic behavior Up to 20% Faster (ave. 5%) Retiming is timing based 4 Retiming  Retiming in the Synplify Pro tool is register balancing  Registers moved across combinatorial logic to improve timing  Timing driven  Glob