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- 2020-01-29 发布于辽宁
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9.1 A simple example in VHDL If we want to check that our description is functioning correctly, we can feed it into a simulator, a program that predicts how the outputs would change in response to changes in the input. * 9.1 A simple example in VHDL 3. BEGIN and END statements VHDL uses the keywords BEGIN and END to indicate the beginning and end of a block respectively. 4. Semicolons VHDL uses the semicolon to indicate the end of a statement. * 9.2 Stylistic issues 1. Case VHDL is not case sensitive. 2. Spaces and indents Any number of spaces can be used between words without affecting the meaning of the code. 3. Returns Putting in a carriage return makes no difference to the function of the code. * 9.2 Stylistic issues 4. Annotating END statements In a long description, in order to keep track, we can put the name of what we intend to end after the END statement. ENTITY nandgate IS PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC); END ENTITY nandgate; ARCHITECTURE simple OF nandgate IS BEGIN c = a NAND b; END ARCHITECTURE simple; * 9.2 Stylistic issues 5. Comments Comments are text that we introduce into the VHDL description in order to help a person reading to the code to understand what is happening. Comments are introduced by two dashes. Everything between the two dashes and the end of line is regarded as a comment. * 9.3 The IEEE library 1. Opening libraries A large number of features and extensions to the capabilities of the VHDL language are bundled into a library called “IEEE”. The IEEE library is made available by the statement: LIBRARY IEEE; The IEEE library contains many sub-libraries, which in turn contain many features. VHDL sub-libraries are called packages. * 9.3 The IEEE library In order to say which features of which packages we wish to access, we use : USE IEEE.XXXX.YYYY XXXX is the name of the required package YYYY is the name of the specific feature that is to be used USE IEEE.XXXX.ALL Often we simply ma
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