《可编程逻辑器件及应用》课程设计报告完整.docxVIP

摘 要 本课程设计给出了一种基于 FPGA 的多功能数字时钟方法，采用 EDA 作为开 发工具，VHDL 语言和图形输入为硬件描述语言，Quartus II 9.0 作为运行程序 的平台，编写的程序经过调试运行，波形仿真验证，下载到 EDA 实验箱的 FPGA 芯片，实现了设计目 该系统主要由分频模块、控制模块、计时模块、显示模块组成。经编译和 仿真所设计的程序，在可编程逻辑器件上下载验证，能够在数码管上完成年、 月、日和时、分、秒的分别显示，由按键输入进行数字时钟的校时、清零、暂 停功能。 关键词：EDA 技术；FPGA；数码管 Abstract The course design gives a FPGA-based multifunctional digital clock using EDA as a development tool, VHDL language and graphical input hardware description language, the Quartus II 9.0 as a platform for running the program, written procedures debugging and running, the waveform simulation downloaded to the FPGA chip to achieve the design goals. The design for a multi-functional digital clock, with a year, month, day, hours, minutes and seconds count display to a 24-hour cycle count, with the pause time, clear function and the hours and minutes setting function. The main system is made up of frequency module, control module, time module, display module. After compiling the design and simulation procedures, the programmable logic device to download verification, the system can complete the year, month, day and the hours, minutes and seconds respectively, using keys to modify, clear , start and stop the digital clock. Key words：EDA technology; FPGA; digital clock; VHDL language; digital tube 目 录 1 绪论 ...........................................................................................................................................................1 1.1 1.2 课程背景 ............................................................................................................................................1 设计目的 ............................................................................................................................................1 2 总体设计流程说明 ...................................................................................................................................2 2.1 数字时钟的工作原理 ........................................................................................