采用TSMC 7nm工艺技术的下一代大规模芯片的PI Signoff挑战和解决方案.pdfVIP

Challenges and Solutions of PI Signoff for Next Generation Large Scale Chips with TSMC 7nm Process Technology Junjie Chen, Keqing Ouyang ZTE SANECHIPS 2019/10/29 CONTENTS • General Overview of Sanechips • Backgrounds and Motivations • Solutions of New Technology Challenges • Summary General Overview of Sanechips • 20+ years in IC developments Re-organized as an independent legal entity in 2003 • Leading Chip provider in industry with 1800+ employees in 8 RD centers • Advanced physical design capability with cutting-edge process technology • 100+ chips in mass production, with board portfolio covering cloud, pipeline and terminals • 3500+ patents owned including 1700+ international patents © ZTE All rights reserved 3 Backgrounds and Motivations • Design challenges on IREM ✓ Evolution process technology ➢ Decreasing supply voltage ➢ Demanding PVT corner coverage due to reduced PI noise margin ➢Significant self-heating effect ✓ Increasing design scale and complexity ➢Single machine needs larger memory ➢ Legacy multi-threads solution cannot meet PI simulation requirements ➢ More functional scenes need to be simulated ➢Vector-based PI simulation becomes more and more difficult 6X Increase in grid • Challenges in IREM signoff complexity, compared to Ultra low voltage computing ✓ Resistance,nodes and local power density are increasing 16nm. Power grids have means margins are razor thin,