EDA技术应用 7.2.4xilinx原版课件 floorplanner_adv_8.pptVIP

Floorplanner: Effective Layout Objectives Identify the Floorplanner windows Specify the Floorplanner flow Describe how to use area constraints Identify how PACE is used to specify area constraints Identify optimal pin layout Outline Introduction Floorplanning Procedures Area Constraints I/O Layout Summary Appendix: RPM Core Overcoming MAP/PAR Limitations Pseudo Guide File with Floorplanner Additional I/O Considerations What is the Floorplanner? Graphical tool used to display/edit design layout Easy to review the results of implementation When to Floorplan Use the Floorplanner to: Increase productivity/design performance View the layout of your implemented design Partition design sub-systems into general areas on the die (area constraints/layout) Make minor placement modifications Create RPMs (Relationally Placed Macros) Use the Floorplanner carefully Poor floorplanning can decrease design performance The implementation tools cannot disregard a poor floorplan Floorplanner Prerequisites Do not perform significant floorplanning unless you are very familiar with: The design The target device architecture Xilinx software Without sufficient knowledge, it is suggested you try the following first Use timing constraints Increase Place Route Effort Level Specify ? Perform Timing-Based Packing (Map) and extra-effort level (PAR) Pipeline or redesign logic in critical paths Use re-entrant routing or MPPR Floorplanning Advantage: Given sufficient knowledge… In large and/or high performance designs, floorplanning/layout is an effective precursor to implementation Provides guidance to implementations tools on the layout of the design Can help to reduce run time Can help to increase performance Floorplanning is required for Incremental Design Techniques and Modular Design Techniques Floorplanning Flow Floorplanner Versus PACE PACE: Easiest tool for specifying pin placement constraints and area constraints Floorplanner: More advanced tool with placement capabilities beyond