tms320f2812-标准资料文件.pdf

SPRS174D – APRIL 2001 – REVISED APRIL 2002 High-Performance Static CMOS Technology Motor Control Peripherals – 150 MHz (6.67-ns Cycle Time) – Two Event Managers (EVA, EVB) – Low-Power (1.8-V Core, 3.3-V I/O) Design – Compatible to 240x Devices – 3.3-V Flash Programming Voltage Serial Port Peripherals JTAG Boundary Scan Support† – Serial Peripheral Interface (SPI) High-Performance CPU (TMS320C28x) – Two Serial Communications Interfaces – 16 x 16 and 32 x 32 MAC Operations (SCIs), Standard UART – 16 x 16 Dual MAC – Enhanced Controller Area Network – Harvard Bus Architecture (eCAN) – Atomic Operations – Multichannel Buffered Serial Port – Fast Interrupt Response and Processing (McBSP) With SPI Mode – Unified Memory Programming Model 12-Bit ADC, 16 Channels – 4M Linear Program Address Reach – 2 x 8 Channel Input Multiplexer – 4M Linear Data Address Reach – Two Sample-and-Hold – Code-Efficient (in C/C++ and Assembly) – Single Conversion Time: 200 ns – TMS320F24x/LF240x Processor Source – Pipeline Conversion Time: 60 ns Code Compatible Up to 56 Individually Programmable, On-Chip Memory Multiplexed Gen