fpga可编程逻辑器件芯片ep4sgx290fh29c4中文规格书.docxVIP

External Memory Interfaces in Stratix II and Stratix II GX Devices Table 3-5. Stratix II GX DQS and DQ Bus Mode Support Note (1) Device Package Number of x4 Groups Number of x8/x9 Groups Number of x16/x18 Groups Number of x32/x36 Groups EP2SGX30C EP2SGX30D 780-pin FineLine BGA 18 8 4 0 EP2SGX60C EP2SGX60D 780-pin FineLine BGA 18 8 4 0 EP2SGX60E 1,152-pin FineLine BGA 36 18 8 4 EP2SGX90E 1,152-pin FineLine BGA 36 18 8 4 EP2SGX90F 1,508-pin FineLine BGA 36 18 8 4 EP2SGX130G 1,508-pin FineLine BGA 36 18 8 4 Note to Table 3-5: (1) Check the pin table for each DQS/DQ group in the different modes. Table 3-6. Stratix II GX Non-DQS and DQ Bus Mode Support Note (1) Device Package Number of x4 Groups Number of x8/x9 Groups Number of x16/x18 Groups Number of x32/x36 Groups EP2SGX30 780-pin FineLine BGA 18 8 4 2 EP2SGX60 780-pin FineLine BGA 18 8 4 2 1,152-pin FineLine BGA 25 13 6 3 EP2SGX90 1,152-pin FineLine BGA 25 13 6 3 1,508-pin FineLine BGA 25 12 6 3 EP2SGX130 1,508-pin FineLine BGA 25 12 6 3 Note to Table 3-6: (1) Check the pin table for each DQS/DQ group in the different modes. L To support the RLDRAMIIQVLD pin, some of the unused x4 DQS pins, whose DQ pins were combined to make the bigger x8/x9, xl6/xl8, or x32/x36 groups, are listed as DQVLD pins in the Stratix II or Stratix II GX pin table. DQVLD pins are for input-only operations. The signal coming into this pin can be captured by the shifted DQS signal like any of the DQ pins. Tables 1-20 and 1-21 show which PLLs are available in each Stratix II and Stratix IIGX device, respectively, and which input clock pin drives which PLLs. Table 1-20. Stratix II Device PLLs and PLL Clock Pin Drivers (Part 1 of 2) Input Pin All Devices EP2S60 to EP2S180 Devices Fast PLLs Enhanced PLLs Fast PLLs Enhanced PLLs 1 2 3 4 5 6 7 8 9 10 11 12 CLKO ，（1） CLK1 (2) V /⑴ CLK2 /⑴ ，(1) CLK3 (2) /⑴ /⑴ CLK4 CLK5 CLK6 CLK7 CLK8 / CLK9 (2) 5 CLK10 V /⑴ CLK11 (2) /⑴ /⑴ CLK12 CLK13 CLK14 CLK15 PLL5FB PLL6FB PLL11FB PLL12FB PLLENA / / / FPLL7CLK (2)