fpga可编程逻辑器件芯片ep4sgx290kf40i2n中文规格书.docxVIP

Therefore, placing ground planes close to a signal source reduces inductance and helps contain EML Figure 11-36 shows an example of an eight-layer stack-up. In the stack-up, the stripline signal layers are the quietest because they are centered by power and GND planes. A solid ground plane next to the power plane creates a set of low ESR capacitors. With integrated circuit edge rates becoming faster and faster, these techniques help to contain EML Figure 11-36. Example Eight-Layer Stack-Up Signal Ground Signal Power Ground Signal Ground Signal Component selection and proper placement on the board is important to controlling EML The following guidelines can reduce EMI: Select low-inductance components, such as surface mount capacitors with low ESR, and effective series inductance. Use proper grounding for the shortest current return path. Use solid ground planes next to power planes. In unavoidable circumstances, use respective ground planes next to each segmented power plane for analog and digital circuits. Additional FPGA-Specific InformationThis section provides the following additional information recommended by Altera for board design and signal integrity: FPGA-specific configuration, Joint Test Action Group (JTAG) testing, and permanent test points. Additional FPGA-Specific Information Configuration The DCLK signal is used in configuration devices and passive serial (PS) and passive parallel synchronous (PPS) configuration schemes. This signal drives edge-triggered pins in Altera devices. Therefore, any overshoot, undershoot, ringing, crosstalk, or other noise can affect configuration. Use the same guidelines for designing clock signals to 芯片详细信息 Manufacturer Part Number: EP4SGX290KF40I2N Package Description: BGA. Manufacturer Altera Corporation Number of CLBs: 116480 Package Code: BGA Seated Height-Max: 3.6 mm Terminal Position: BOTTOM Part Life Cycle Code: Transferred Pin Count 1517 Risk Rank Number of Terminals: 1517 Package Shape: SQ