fpga可编程逻辑器件芯片ep4sgx290kf40i3n中文规格书.docxVIP

Figure 76- Reset Block Diagram with Single Reset Control resettx reset txready The Intel Quartus Prime Pro Edition software detects the presence of instantiated transceiver Native PHY IP cores and automatically inserts the TRS. The txreset and rxreset inputs, either generated by you or through the reset controller, are received by the Local TRS. The Local TRS also forwards the request to the master TRS for scheduling. TRSs work together to schedule all the requested RS-FEC/PMAIF resets and provide acknowledgment for each request. Use either the reset controller inside the transceiver PHY or your own reset controller with the transceiver reset in manual mode. However, for the TRS to work correctly, the required timing duration must be followed. Note: The master and local TRS IP is an inferred block and is not visible in the RTL. You have no control over this block. Table 59. Reset Signals Required for E-Tile Reset Transceiver Reset Category txreset TX EMIB reset EMIB Reset TX PMAIF reset Transceiver Interface Reset RS-FEC reset RS-FEC Reset TX RS-FEC reset General RS-FEC reset and includes the TX and RX datapath rxreset RX EMIB reset EMIB Reset RX PMAIF reset Transceiver Interface Reset RX RS-FEC reset RS-FEC Reset on RX datapath The txreset and rxreset signals apply the associated transceiver resets. You can use the Native PHYs Avalon memory-mapped interface to do a PMA analog reset or to enable and disable the PMA. You have the option to use txreset and rxreset as the input controls if you enable independent TX and RX reset, or you can use reset as the input to control both TX and RX if you disable independent TX and RX reset. The diagrams Reset 芯片详细信息 Manufacturer Part Number: EP4SGX290KF40I3N Pbfree Code: O Yes Rohs Code: ?Yes Part Lrfe Cycle Code: Transferred Ihs Manufacturer Part Package Code: Package Description Pin Count: ALTERA CORP BGA LEAD FREE. FBGA-1517 1517 Reach Compliance Code: HTS Code: Manufacturer Risk Rank: notcompliant Altera Corporation Clock F