memory存储芯片np5q128a13esfc0e中文规格书.docxVIP

General Description Micron NAND Flash devices include an asynchronous data interface for high-performance I/O operations. These devices use a highly multiplexed 8-bit bus (DQx) to transfer commands, address, and data. There are five control signals used to implement the asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control hardware write protection (WP#) and monitor device status (R/B#). This Micron NAND Flash device additionally includes a synchronous data interface for high-performance I/O operations. When the synchronous interface is active, WE# becomes CLK and RE# becomes W/R#. Data transfers include a bidirectional data strobe (DQS). This hardware interface creates a low pin-count device with a standard pinout that remains the same from one density to another, enabling future upgrades to higher densities with no board redesign. A target is the unit of memory accessed by a chip enable signal. A target contains one or more NAND Flash die. A NAND Flash die is the minimum unit that can independently execute commands and report status. A NAND Flash die, in the ONFI specification, is referred to as a logical unit (LUN). For further details, see Device and Array Organization. Asynchronous and Synchronous Signal Descriptions Table 1: Asynchronous and Synchronous Signal Definitions Asynchronous Signal1 Synchronous Signal1 Type Description2 ALE ALE Input Address latch enable: Loads an address from DQx into the address register. CE# CE# Input Chip enable: Enables or disables one or more die (LUNs) in a target1. CLE CLE Input Command latch enable: Loads a command from DQx into the command register. DQx DQx I/O Data inputs/outputs: The bidirectional I/Os transfer address, data, and command information. DQS I/O Data strobe: Provides a synchronous reference for data input and output. RE# W/R# Input Read enable and write/read: RE# transfers serial data from the NAND Flash to the host system when the asynchronous interface is active. When t