快速高效的MAC单元在FPGA上的实现(IJMSC-V2-N4-3).pdfVIP

I.J. Mathematical Sciences and Computing, 2016, 4, 24-33 Published Online November 2016 in MECS () DOI: 10.5815/ijmsc.2016.04.03 Available online at /ijmsc Implementation of Fast and Efficient Mac Unit on FPGA a a Sachin Raghav , Dr. Rinkesh Mittal aCEC Landran, Mohali/ECE Dept, Chandigarh, 140307, India Abstract Floating-point arithmetic operations on digital systems have become an important aspect of research in recent times. Many architecture have been proposed and implemented by various researchers and their merits and demerits are compared. Floating point numbers are first converted into the IEEE 754 single or double precision format in order to be used in the digital systems. The arithmetic operations require various steps to be followed for the correct and accurate steps. In the proposed approach a fast and area efficient Carry Select Adder are implemented along with the parallel processing of various units used in the architecture. The result also verifies the proposed approach that shows a decrement of 27 % in the combinational path delay with an increment of around 8% in the number of LUTs used. Index Terms: MAC Unit, FPGA, FMA . © 2016 Published by MECS Publisher. Selection and/or peer review under responsibility of the Research Association of Modern Education and Computer Science 1. Introduction In DSP applications the floating-point FMA instruction is currently available in many general-purpose processors. It enhances its performance by decreasing the latency factor and increases the level of accuracy with no intermediate routing. Most of the processors like intel, IBM has involves the fused multiply fused unit in its FP uni