51扩展板电路原理图.docxVIP

VCC P07 D271 P06 D260 P05 D159  U5 msb2-1 2-2 2-3  IN-0 IN-1  VCC 26 27  VCC R5 JP1 AT89S51 R9 R10 R11 R12 R13 R14 R15 R16 1K 1K 1K 1K 1K 1K 1K 1K  U3C P04 D148 P03 D38 P02 D125 P01 D14 P00 D107 2-4 2-5 2-6 2-7 lsb2-8 IN-2 28 IN-3 1 10K J2 1 2 VCC C1  U1 DS1302 P10 P11 1 2 P12 3 4 5 6 VCC P00 P01 8 P32 IN1T00 9 7 EOC IN-4 2 IN-5 3 IN3 20pF C2 20pF Y1 32.768KHz VCC2 VCC1 8 X1 SCLK 7 X2 IO 6 GND RST 5 VCC P10 P11 P12 P13 7 8 P14 9 10 P15 11 12 P16 13 14 P17 15 16 RST 17 18 P30 RXD P31 TXD 19 20 P32 INT0 21 22 P33 INT1 23 24 25 26 EA ALE PSEN P27 P02 P03 P04 P05 P06 P07  P36 WR2 3 P27 5 74LS02 U3A 1 74LS02 U3B P00 A25 P01 B24 P02 C23 22 9 6 10 ADD-A ADD-B ADD-C ALE ENABLE START CLOCK IN-6 4 IN-7 5 ref(-) 16 ref(+) 12 J3 1 2 IN6 C3 0.1UF U2 NC A1  VCC WP R2 R3 4.7K 4.7K 8 7 R4 4.7K  P20 P34 T0 P35 T1 P36 WR P37 RD X2 X1 GND 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P26 P25 P24 P23 P22 P21 P20  VCC 0 1  U4B  P37  RD6 2  74LS02 D  VCC 4 PRE Q 4 U4A 5 ADC0809  VCC A2 GND AT24C04 SCL 6 SDA 5 P21 P22 12 ALE 11 D CLK PRE Q 9 3 CLK 6 CLR Q CLR Q 8 74LS74 74LS74 1 3 VCC 1 VCC VCC J5 1 TXOUT 6 RXIN 2 7 3 8 4  VCC 6 1 12 R1 OUCT 9 C 14 R2 OUVT 7 T1 OUT 4 T2 OUT 5 C2+ C2 -  C5 0.1UF 6 2 V- + R1 IN V V R2 IN T1 IN T2 IN D C1+ GN C1 - G  C4 0.1UF 13 8 11 10 1 3  TXD RXD  P31 P30  P00 P01 P02 P03 P04 P05 P06 P07 P23 D0 7 D1 6 D2 5 D3 4 D4 16 D5 15 D6 14 D7 13 CS lsbDI0 DI1 DI2 DI3 DI4 DI5 DI6 msbDI7  VCC 0 2 c V  Iout1 Iout2 Rfb Vref ILE  11 12 9 VCC 8 VCC 19  -VCC 4 2 3 8  U7A 1 R6 1K LM358 R7 2K  R8 2K U7B 6 5 LM358  7 OUT  J4 1 2 OUT 9 C7 U8 MAX232 C6 P36 1 CS WR2 18 VCC U9 MAX860 5 DB9 0.1UF 5 1 0.1UF 17 Xfer U6 DAC0832 WR WR1 2 C9 10uF 1 FC 2 C1+ 3 GND 4 C1- VDD 8 SH 7 LV 6 OUT 5 VCC -VCC C8 10uF VCC C10 47UF  C11 0.1UF  VOUT R1 10K  VCC  VSS VDD V0 P24 RS/CS P25 RW/SID P26 E/SCLK P00