eda实验报告分析和总结.docxVIP

实验一LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ADDER IS PORT(A,B:IN STD_LOGIC_VECTOR(15 downto 0); SUM:OUT STD_LOGIC_VECTOR(15 downto 0)); END ADDER; ARCHITECTURE behav OF ADDER IS BEGIN SUM=(A+B); END behav; 实验二 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUX4 IS PORT(A,B:IN STD_LOGIC_VECTOR(3 downto 0); SEL:INTEGER RANGE 0 TO 1; Y:OUT STD_LOGIC_VECTOR(3 downto 0)); END MUX4; ARCHITECTURE behav OF MUX4 IS BEGIN WITH SEL SELECT Y=A WHEN 0, B WHEN 1; END behav; 实验三 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY SEVEN IS PORT(INPUT:IN std_logic_vector( 2 DOWNTO 0); A,B,C,D,E,F,G:OUT std_logic); END SEVEN; ARCHITECTURE behav OF SEVEN IS BEGIN PROCESS(INPUT) BEGIN CASE INPUT IS WHEN 000=A=1;B=1;C=1;D=1;E=1;F=1;G=0; WHEN 001=A=0;B=1;C=1;D=0;E=0;F=0;G=0; WHEN 010=A=1;B=1;C=0;D=1;E=1;F=0;G=1; WHEN 011=A=1;B=1;C=1;D=1;E=1;F=0;G=1; WHEN OTHERS=A=1;B=0;C=0;D=1;E=1;F=1;G=1; END CASE; END PROCESS; END behav; 八到十六位移位器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SHIFTER IS PORT(input:IN STD_LOGIC_VECTOR(7 DOWNTO 0); cnt:IN STD_LOGIC_VECTOR(1 DOWNTO 0); result:OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END SHIFTER; ARCHITECTURE BEHAV OF SHIFTER IS BEGIN PROCESS(input,cnt) BEGIN IF cnt=00 THEN FOR i IN 0 TO 15 LOOP IF i7 THEN result(i)=0; ELSE result(i)=input(i); END IF; END LOOP; ELSIF cnt=01 THEN FOR i IN 0 TO 15 LOOP IF i4 THEN result(i)=0; ELSIF i11 THEN result(i)=0; ELSE result(i)=input(i-4); END IF; END LOOP; ELSIF cnt=10 THEN FOR i IN 0 TO 15 LOOP IF i8 THEN result(i)=input(i-8); ELSE result(i)=0; END IF; END LOOP; ELSIF cnt=11 THEN FOR i IN 0 TO 15 LOOP IF i=8 and i=15 THEN result(i)=0; ELSE result(i)=input(i); END IF; END LOOP; END IF; END PROCESS; END BEHAV; 十六位同步寄存器 LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_unsigned.all; ENTITY reg IS PORT ( clk, clken, clr : IN std_logic; in_reg : IN std_logic_vector(15 downto 0); out_reg : OUT std_logic_vector(15 downto 0)); END reg;