Intel英特尔MAX® 10 外部内存接口用户指南.pdf

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Altera®DesignHub

®

MAX10ExternalMemoryInterface

UserGuide

®

UpdatedforQuartusPrimeDesignSuite:24.1

OnlineVersion683087

SendFeedbackUG-M10EMI2025.03.17

Contents

Contents

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1.MAX10ExternalMemoryInterfaceOverview4

1.1.MAX10ExternalMemoryInterfaceSupportandPerformance5

2.MAX10ExternalMemoryInterfaceArchitectureandFeatures6

2.1.MAX10I/OBanksforExternalMemoryInterface6

2.2.MAX10DQ/DQSGroups7

2.3.MAX10ExternalMemoryInterfacesMaximumWidth8

2.4.MAX10MemoryController9

2.5.MAX10ExternalMemoryReadDatapath10

2.5.1.DDRInputRegisters11

2.6.MAX10ExternalMemoryWriteDatapath12

2.6.1.DDROutputRegisters12

2.7.MAX10Address/CommandPath14

2.8.MAX10PHYClock(PHYCLK)Network15

2.9.PhaseDetectorforVTTracking15

2.10.On-ChipTermination16

2.11.Phase-LockedLoop16

2.12.MAX10LowPowerFeature17

3.MAX10ExternalMemoryInterfaceDesignConsiderations18

3.1.MAX10DDR2andDDR3DesignConsiderations18

3.1.1.DDR2/DDR3ExternalMemoryInterfacePins18

3.1.2.DDR2/DDR3RecommendedTerminationSchemesforMAX10Devices20

3.2.LPDDR2DesignConsiderations21

3.2.1.LPDDR2ExternalMemoryInterfacePins21

3.2.2.LPPDDR2PowerSupplyVariationConstraint23

3.2.3.LPDDR2RecommendedTerminationSchemesforMAX10Devices23

3.3.Guidelines:DDR3,DDR2,andLPDDR2ExternalMemoryInterfaceI/OLimitation23

3.4