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Abstract
With the rapidly progressing Integrated Circuit (IC) technology, the functional
verification becomes the bottleneck of development for Application-Specific
Integrated Circuits (ASIC). Since a complete verification methodology, such as
formal verification, is very difficult to apply in real-life cases, simulation-based
verification is one of the most frequently used methodologies for the functional
verification. Most designers agree that as much as 70 percent of the design cycle is
consumed by the functional verification. Therefore, an effective verification method is
critical for maintaining the time to market and reducing design cost.
This thesis illustrates a Verification Intellectual Property (VIP) method. The
characteristics of this VIP are re-useable to build engineers confidence in their
designs. This VIP is composed of a transaction-based method to build Bus Function
Models (BFM), a simulation-based method to simulate the function of the design with
the testbenches and an assertion-based method to calculate the function coverage. For
massive data transaction simulations, the VIP described uses Programming Language
Interface (PLI) to better manage memory usage and effectively reduce simulation time.
Using Verilog and PLI to implement BFM is convenient for engineers to maintain it
without studying other language and economical to need no other simulator.
iv
With the gradually increasing complexity and powerful performance of the
Integrated Circuit (IC), more and more engineers pay attention to increase hardware
resource utilization, and virtualization technologies is one of these approaches.
Recently, Peripheral Component Interconnect Spe
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