IEEE80211n无线局域网中的多模交织研究与实现.pdfVIP

第 40 卷 第 3 期 电 子 科 技 大 学 学 报 Vol.40 No.3 20 11年5月 Journal of University of Electronic Science and Technology of China May 20 11 IEEE 802.11n无线局域网中的多模交织研究与实现 张振东，吴 斌，朱勇旭，周玉梅 ( 中国科学院微电子研究所 北京 朝阳区 100029) 【摘要】对IEEE 802.11n协议中交织与解交织的置换规律进行了研究，提出一种支持该协议全部36种交织模式的交织器硬 件结构。设计技术包括：合并三次置换为一次写、读数据操作；利用置换的循环特性设计优化电路代替复杂的计算公式，产 生多模地址及复用交织与解交织。FPGA 实现及ASIC综合仿真结果说明，该结构相对于已有的设计能够获得更高的速度并减 少芯片面积与功耗开销。在SMIC 0.13 mm CMOS工艺下其综合的最高工作频率为400 MHz ，对应的功耗为10.8 mW ，面积为 2 0.066 7 mm 。 关 键 词 解交织；交织；复用；多输入多输出；无线局域网 中图分类号 TN911 文献标识码 A doi:10.3969/j.issn.1001-0548.2011.03.011 Design and Implementation of Multi-Mode Interleaver for IEEE 802.11n WLAN ZHANG Zhen-dong, WU Bin, ZHU Yong-xu, and ZHOU Yu-mei (Institute of Microelectronics, Chinese Academy of Sciences Chaoyang Beijing 100029) Abstract In the multiple-input multiple-output (MIMO) orthogonal frequency-division multiplexing based systems, interleaver and deinterleaver with multi-mode and high-speed are required. In this paper, a novel 36-mode interleaver fully compliant to IEEE 802.11n wireless local area network (WLAN) protocol is presented. Three design techniques are proposed : merging permutations, replacing arithmetic expressions with optimized circuits, and multiplexing interleaver/deinterleaver. The proposed design is implemented in both FPGA and ASIC. It achieves a reduction of silicon area and power consumption when compared with other similar works. In SMIC 0.13 mm CMOS technology, the maximal operating frequency is synthesized 400 MHz and the corresponding 2 power di