2014年ARM微处理器体系结构.pptVIP

SWI异常 SWI 0x01 向量表 用户程序 (C/ASM) SWI 处理程序 (ASM) （可选） SWI 处理程序 (C) 用户程序调用 SWI SWI 中断处理程序包含汇编部分和可选用的 C 部分 软件中断指令 当ARM7TDMI处理器遇到一条自己和系统内任何协处理器都无法处理的指令时，ARM7TDMI内核执行未定义指令陷阱。软件可使用这一机制通过模拟未定义的协处理器指令来扩展ARM指令集。 注：ARM7TDMI处理器完全遵循ARM结构v4T，可以捕获所有分类未被定义的指令位格式。 未定义指令异常 在模拟处理了失败的指令后，陷阱程序执行下面的指令： MOVS PC,R14_svc 这个动作恢复了PC、CPSR并返回到未定义指令之后的指令。 未定义指令异常 未定义的指令 谢 谢 各 位 * * * This slide is aimed at showing the development of the ARM Architecture. The “Stars” mark each relevant Architecture Level. The “Boxes” give examples of ARM products implementing each particular Architecture level. This is not meant to be a complete list of products, what they offer, or a product roadmap. Within each Architecture The “Notes by the Stars” give the major enhancements specified by this particular Architecture over the previous one. Note architectures 1,2,3 have been removed - these are obsolete (the only part which contains arch 3 core is ARM7500FE). ARM1020T was architecture v5T, however we are rapidly transitioning to ARM1020E and 1022E. Jazelle adds Java bytecode execution, which increases Java performance by 5-10x and also reduces power consumption accordingly. 9EJ - Harvard - 200MIPS 7EJ - Von Neumann - 70MIPS Brief notes on V6: SIMD instructions provide greatly increased audio/video codec performance LDREX/STREX instructions improve multi-processing support VMSA (Virtual Memory System Architecture): Complete L1 cache and TCM definition; physically-tagged cache; ASID for improved task-switching SRS and RFE instructions to improve exception handling performance Hardware and instruction set support for mixed-endianness 1136JF-S has integral VFP coprocessor * * * * * * * * * * * * * * 系统：System mode, only present in ARM V4 and above. It is not entered by any exception and has exactly the same registers available as User mode. However, it is a privileged mode and is therefore not subject to the User mode restrictions. It is intended for use by