EE466 VLSIDesignLecture 7 Circuits amp; Layout.ppt

1: Circuits Layout EE466: VLSIDesignLecture 7: Circuits Layout Outline CMOS Gate Design Pass Transistors CMOS Latches Flip-Flops Standard Cell Layouts Stick Diagrams CMOS Gate Design Activity: Sketch a 4-input CMOS NAND gate CMOS Gate Design Activity: Sketch a 4-input CMOS NOR gate Complementary CMOS Complementary CMOS logic gates nMOS pull-down network pMOS pull-up network a.k.a. static CMOS Series and Parallel nMOS: 1 = ON pMOS: 0 = ON Series: both must be ON Parallel: either can be ON Conduction Complement Complementary CMOS gates always produce 0 or 1 Ex: NAND gate Series nMOS: Y=0 when both inputs are 1 Thus Y=1 when either input is 0 Requires parallel pMOS Rule of Conduction Complements Pull-up network is complement of pull-down Parallel - series, series - parallel Compound Gates Compound gates can do any inverting function Ex: Example: O3AI Example: O3AI Signal Strength Strength of signal How close it approximates ideal voltage source VDD and GND rails are strongest 1 and 0 nMOS pass strong 0 But degraded or weak 1 pMOS pass strong 1 But degraded or weak 0 Thus nMOS are best for pull-down network Pass Transistors Transistors can be used as switches Pass Transistors Transistors can be used as switches Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well Tristates Tristate buffer produces Z when not enabled Tristates Tristate buffer produces Z when not enabled Nonrestoring Tristate Transmission gate acts as tristate buffer Only two transistors But nonrestoring Noise on A is passed on to Y Tristate Inverter Tristate inverter produces restored output Violates conduction complement rule Because we want a Z output Tristate Inverter Tristate inverter produces restored output Violates conduction complement rule Because we want a Z output Multiplexers 2:1 multiplexer chooses between two inputs Multipl