VHDL8 Practical example v5c.ppt

VHDL8 Practical example v5c * Exercise 8.6 Fill in the modes (in, out, inout or buffer) of the input/output signal. SRAM (memory) CPU address lines (A0-A16) data lines (D0-D7) /CS,/OE and /WE lines VHDL8 Practical example v5c * Exercise 8.7 Referring to the figure, what would happen if /RD of the CPU (connected to /OE) goes up before the data valid region occurs? tRC ADD /CE Or (/CS) /OE DOUT VHDL8 Practical example v5c * Exercise 8.8 : Referring to the Figure, if tAS=0ns, twc=100ns,tCW=80ns, give comments on the limits of tAW, tWP and tDW.. ADD /CE Or (/CS) /WE DIN tWC tCW tAW tDW tWP VHDL8 Practical example v5c * Part 2 The Logic Analyzer The Logic Analyzer Overall diagram VHDL8 Practical example v5c * Xilinx based hardware ARM7 board RAM Reset Rec Play DA_in[7..0] DA_out[7..0] Serial port Display waveform VHDL8 Practical example v5c * Memory (32K) interface entity logic_rec is Port ( clk40k_in: in std_logic; reset: in std_logic; rec, play: in std_logic; --user inputs -- mem RAM bus bar_ram_we27: out std_logic; bar_ram_cs20: out std_logic; bar_ram_oe22: out std_logic; -- 32k-byte ram_address_buf: buffer std_logic_vector(14 downto 0); ram_data_inout: inout std_logic_vector(7 downto 0); da_data_out: buffer std_logic_vector(7 downto 0); da_data_in: in std_logic_vector(7 downto 0)); end logic_rec; VHDL8 Practical example v5c * Static memory (SRAM 32Kbytes) data pins Diagrams are obtained from data sheet of HM62256B VHDL8 Practical example v5c * HM62256B Memory read timing diagrams VHDL8 Practical example v5c * HM62256B Write mode timing diagram Flow diagram VHDL8 Practical example v5c * s_init s_rec_address_change s_rec_read_from_da_to_reg1 s_rec_we_cs_down s_rec_writeto_da_ram s_play_address_change s_play_cs_oe_down s_play_read_in_reg1 s_play_writeto_da ram_address_buf =not all’1’ ram_address_buf =all’1’ ram_address_buf =not all’1’ rec=‘0’ play=‘0’ reset=‘0’ VHDL8 Practical example v5c * Architecture architecture Behavioral